View ML7204-001_1280484.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML7204-001
VoIP CODEC
FEDL7204-001DIGEST-01
Issue Date: Aug. 12, 2004
GENERAL DESCRIPTION
The ML7204-001 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of G.729.A/G711 and supports the PLC (Packet Loss Concealment) function. With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and tone detection/generation functions, the ML7204-001 is the most suitable LSI for adding the VoIP function to TAs and routers.
FEATURES
* Power supply voltage Digital power supply voltage (DVDD0, 1, 2): 3.0 to 3.6 V Analog power supply voltage (AVDD): 3.0 to 3.6 V * Speech CODEC: G.729.A (8 kbps)/G.711 (64 kbps) -law and A-law (supports individual setting for transmission and reception) Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function Supports the 2-channel processing function (for 3-way communication) * Built-in FIFO buffer (640 bytes) for transmission/reception data transfer Allows selection of Frame/DMA (slave) interface * Echo canceler for handling 32 ms delay * DTMF detection * DTMF generation (the tone generation function enables generation of DTMF signals) * Tone detection: 2 types (1650 Hz and 2100 Hz: Detection frequency can be changed) * Tone generation: 2 types * FSK detection * FSK generation * Built-in 16-bit timer: 1 channel * Dial pulse detection function (secondary function of general-purpose I/O ports) * Dial pulse transmission function (secondary function of general-purpose I/O ports) * General-purpose I/O ports 64-pin package: Equipped with 7 ports (with some of them having secondary function allocation) 100-pin package: Equipped with 21 ports (with some of them having secondary function allocation) * Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B) * Analog interface CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 k driving) CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 k driving) * PCM interface coding format: Allows selection of 16-bit linear/G.711 (64 kbps) -law or A-law * PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output) * PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually) When set to -law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz) When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)
1/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
* Master clock frequency: 12.288 MHz (crystal; external input) * Supports hardware and software power down * Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) 100-pin plastic TQFP (TQFP100-P-1414-0.50-BK)
(ML7204-001GA) (ML7204V-001TB)
2/42
GSX1 TXGAIN_PCM1 PCM_TXEN1 RX_SIG Encoder G.711 P/S TXGAIN _PCM0 SYNC PCM Codec BCLK CLKSEL TS CONT PCM_TXEN0 PCMO PCM I/F LPEN0
CODECB_TXEN
10k
TXDETB
AIN1N
A/D1
BPF
AMP1
TXGAINB
OKI Semiconductor
Linear PCM Codec (CODEC_B) RXGAIN_ITS1 Decoder S/P
CODECB_RXEN
BLOCK DIAGRAM
STGAINB
10k
RXGAINB
VFRO1 RXGAIN_PCM0 RXGAIN_PCM1 PCM_RXEN1 PCM RXEN0
TXGEN
D/A1 RXGAIN_ITS2
LPF
LPEN1
G.711
PCMI
AMP3
RXGENB
GSX0 CH1
TXGAIN_S Sin + LPAD ATTs RX2TX1 _GAIN Center Clip GPAD Sout
10k
TXDETA G.729.A TSW
TXGAIN Encoder _CH1 SC_TXEN
AIN0N
A/D0
BPF
TX Buffer0
AIN0P
-
AMP0
TXGAINA CODECA_TXEN
G.711
TX Buffer1 DC EN Bus Control Unit
ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B CH2 FR0B WRB RDB
MGEN_E XFLAG MGEN_FRFLA TXGAIN _CH2 RX1TX2 _GAIN
Linear PCM Codec (CODEC_A) AF Echo Canceller
STGAINA
Speech Codec
CSB 16b G.729.A Decoder CH1 RX Buffer0 TSW 8b D0-D15 A0-A7
10k Rout CODECA_RXEN SC_RXEN ATTr Rin RXGAIN_SC
RXGAIN
RXGAIN _CH1
VFRO0 RXGEN RXDET
RX_SIG
D/A0
LPF
RXGAIN _CH2
AMP2
CH2
RXGENA
G.711
RX Buffer1
DC_EN
AVREF Various generator paths TXDETA FSK_DET DTMF_REC
TGEN0_EXFL TONE_GEN0 (TONEA/ B) FGEN_FLAG DTMF_CODE[3:0] FDET_D[7:0] DTMF_DET TGEN1_EXFL TONE_GEN1 (TONEC/ D) FDET_RQ FDET_FER/FDET_OER
VREF Various detector paths TXGEN
RXGENA_EN
TIMER DPGEN RXGENA
RXGENB_EN
TIMOVF GPIO2 GPIO0 DPDET
Frame/DMA Controller
DVDD2 TXDETB
DVDD1
Control Register RXGENB RXGEN
DVDD0
DGND2 TONE_DET0
TONE0_DET TONE1_DET
DGND1 TONE_DET1 FSK_GEN
DGND0 RXDET
POWER
PLL
CKGN
MCK
SYNC(8kHz)
AGND
INT
AVDD
INTB/ GPIOA[6]
VREGOUT
OSC 12.288MHz Note: The I/O pins represented by " " can be used for 100-pin packages only.
DP DET DTMF_DET DTMF CODE[3:0] TONE0 DET TONE1_DET DP DET FDET_RQ FDET_FER/FDET_OER FGEN FLAG TIMOVF 8
VGB
4 6
TST1
FEDL7204-001DIGEST-01
XO
[5:0] GPIO
[3:0] GPIO
TST0
PDNB
[7:0] GPIOC
XI
CLKOUT
ML7204-001
3/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN CONFIGURATION (TOP VIEW)
47 GPIOA[2]/DPO 45 GPIOA[0]/DPI
48 GPIOA[3]
46 GPIOA[1]
43 CLKSEL
44 DGND1
AVDD 49 AIN0P 50 AIN0N 51 GSX0
52
33 DVDD1 32 D15 31 D14 30 D13 29 D12 28 D11 27 D10 26 D9 25 D8 24 D7 23 D6 22 D5 21 D4 20 D3 19 D2 18 D1 17 D0
42 PDNB
41 A7
40 A6
39 A5
38 A4
37 A3
36 A2
35 A1
GSX1 53 AIN1N 54 AVREF 55 VFRO0 VFRO1 AGND
56 57 58
DGND2 59 XI
60
XO 61 DVDD2 62 VREGOUT 63 VBG 64 FR0B 10 FR1B 11
12
CSB 13
RDB 14
WRB 15
34 A0
ACK0B/GPIOA[4]
ACK1B/GPIOA[5]
64-Pin Plastic QFP
INTB/GPIOA[6]
DGND0 16
1
2
3
4
5
6
7
8
DVDD0
PCMI
PCMO
BCLK
TST1
TST0
SYNC
9
4/42
AVDD
AIN1N
NC XO NC NC NC NC NC
OKI Semiconductor
VREGOUT AGND NC DGND2 91 DVDD2 95 AVREF 85 VFRO1 87 VFRO0 86 AIN0N 79 AIN0P 78 GSX1 82 GSX0 80 XI 92
98 97 96 94 93 90 89 88 84 83 81 77 76
VBG 99
NC 100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 74
CLKOUT TST1 TST0
75 GPIOA[3]
GPIOA[2]/DPO
73 NC 72 NC 71 GPIOA[1] 70 GPIOA[0]/DPI 69 GPIOB[5] 68 GPIOB[4] 67 DGND1 66 GPIOB[3] 65 GPIOB[2] 64 CLKSEL 63 GPIOB[1] 62 GPIOB[0] 61 PDNB 60 A7 59 A6 58 A5 57 A4 56 A3 55 A2 54 A1 53 A0 52 DVDD1 51 NC 27 D0 28 D1 30 D2 31 D3 33 D4 34 D5 36 D6 37 D7 39 D8 40 D9 26 NC 29 NC 32 NC 35 NC 38 NC 41 NC 44 NC 47 NC 50 NC 43 D11 42 D10 45 D12 46 D13 48 D14 49 D15
GPIOC[0]
GPIOC[1]
PCMO PCMI BCLK
: Provided for 100-pin packages only
SYNC
GPIOC[2]
GPIOC[3]
DVDD0
100-Pin Plastic TQFP
FR0B
19 20
GPIOC[4]
GPIOC[5]
ACK0B/GPIOA[4] 15
ACK1B/GPIOA[5] 16
GPIOC[6] 17
GPIOC[7] 18
FR1B
INTB/GPIOA[6] 21 CSB
22 23 24 25
RDB WRB
FEDL7204-001DIGEST-01
ML7204-001
DGND0
5/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN DESCRIPTIONS
Pin TQFP100 QFP64 1 2 3 4 5 6 7 8 -- 1 2 -- -- 3 4 5 Symbol CLKOUT TST1 TST0 GPIOC[0] GPIOC[1] PCMO PCMI BCLK I/O O I I I/O I/O O I When PDNB = "0" "L" "0" "0" I I "Hi-z" I I I/O "L" I 9 10 11 12 13 14 15 6 -- -- 7 -- -- 8 SYNC GPIOC[2] GPIOC[3] DVDD0 GPIOC[4] GPIOC[5] ACK0B/GPIOA[ 4] I/O "L" I/O I/O -- I/O I/O I/O I I -- I I I Description 12.288 MHz clock output Test control input 1: Normally, input "0". Test control input 0: Normally, input "0". General-purpose I/O port C [0] General-purpose I/O port C [1] PCM data output [Open drain output pin] PCM data input CLKSEL = "0" PCM shift clock input CLKSEL = "1" PCM shift clock output CLKSEL = "0" PCM synchronous signal 8 kHz input CLKSEL = "1" PCM synchronous signal 8 kHz output General-purpose I/O port C[2] General-purpose I/O port C[3] Digital power supply General-purpose I/O port C[4] General-purpose I/O port C[5] Transmit buffer DMA access acknowledge signal input (primary function) General-purpose I/O port A[4] (secondary function) [5 V tolerant pin] Receive buffer DMA access acknowledge signal input (primary function) General-purpose I/O port A [5] (secondary function) [5 V tolerant pin] General-purpose I/O port C [6] General-purpose I/O port C [7] FR0B:(FD_SEL = "0") Transmit buffer frame signal output DMARQ0B: (FD_SEL = "1") Transmit buffer DMA access request signal FR1B: (FD_SEL = "0") Receive buffer frame signal output DMARQ1B: (FD_SEL = "1") Receive buffer DMA access request signal output Interrupt request output (primary function) General-purpose I/O port A [6] (secondary function) [5 V tolerant pin] Chip select control input Read control input Write control input Digital ground (0.0 V)
16 17 18 19
9 -- -- 10
ACK1B/GPIOA[ 5] GPIOC[6] GPIOC[7] FR0B (DMARQ0B)
I/O I/O I/O O
I I I "H"
20
11
FR1B (DMARQ1B)
O
"H"
21 22 23 24 25
12 13 14 15 16
INTB/GPIOA[6] CSB RDB WRB DGND0
I/O I I I --
"H" I I I --
6/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Pin TQFP100 QFP64 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 -- 17 18 -- 19 20 -- 21 22 -- 23 24 -- 25 26 -- 27 28 -- 29 30 -- 31 32 -- -- 33 34 35 36 37 38 39 40 41 Symbol NC D0 D1 NC D2 D3 NC D4 D5 NC D6 D7 NC D8 D9 NC D10 D11 NC D12 D13 NC D14 D15 NC NC DVDD1 A0 A1 A2 A3 A4 A5 A6 A7 I/O -- I/O I/O -- I/O I/O -- I/O I/O -- I/O I/O -- I/O I/O -- I/O I/O -- I/O I/O -- I/O I/O -- -- -- I I I I I I I I
When PDNB = "0" -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- I I -- -- -- I I I I I I I I
Description (Unused) Data input-output Data input-output (Unused) Data input-output Data input-output (Unused) Data input-output Data input-output (Unused) Data input-output Data input-output (Unused) Data input-output. Fix the input to "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). (Unused) Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). (Unused) Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). (Unused) Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). Data input-output. Fix the input "L" or "H" when using the pin in 8-bit bus access (BW_SEL = "1"). (Unused) (Unused) Digital power supply Address input Address input Address input Address input Address input Address input Address input Address input
7/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Pin TQFP100 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 QFP64 42 -- -- 43 -- -- 44 -- -- 45 46 -- -- 47 48 49 -- 50 51 52 -- 53 54 -- 55 56 57 58 -- -- 59 60 -- 61 Symbol I/O
When PDNB = "0" "0" I I I I I -- I I I I -- -- I I -- -- I I "Hi-z" -- "Hi-z" I -- "L" "Hi-z" "Hi-z" -- -- -- -- I -- "H"
Description Power-down input "0": Power-down reset "1": Normal operation General-purpose I/O port B[0] General-purpose I/O port B[1] SYNC/BCLK input-output control input "0": SYNC/BCLK are configured to be input "1": SYNC/BCLK are configured to be output General-purpose I/O port B[2] General-purpose I/O port B[3] Digital ground (0.0 V) General-purpose I/O port B[4] General-purpose I/O port B[5] General-purpose I/O port A[0] [5 V tolerant pin] Secondary function: Input pin for dial pulse detection General-purpose I/O port A[1] [5 V tolerant pin] (Unused) (Unused) General-purpose I/O port A[2] [5 V tolerant pin] Secondary function: Output pin for dial pulse transmission General-purpose I/O port A[3] [5 V tolerant pin] Analog power supply (Unused) AMP0 non-inverting input AMP0 inverted input AMP0 output (10 k driving) (Unused) AMP1 output (10 k driving) AMP1 inverted input (Unused) Analog signal ground (1.4 V) AMP2 output (10 k driving) AMP3 output (10 k driving) Analog ground (0.0 V) (Unused) (Unused) Digital ground (0.0 V) 12.288 MHz crystal interface, 12.288 MHz clock input (Unused) 12.288 MHz crystal interface
PDNB GPIOB[0] GPIOB[1] CLKSEL GPIOB[2] GPIOB[3] DGND1 GPIOB[4] GPIOB[5] GPIOA[0]/DPI GPIOA[1] NC NC GPIOA[2]/DP O GPIOA[3] AVDD NC AIN0P AIN0N GSX0 NC GSX1 AIN1N NC AVREF VFRO0 VFRO1 AGND NC NC DGND2 XI NC XO
I I/O I/O I I/O I/O -- I/O I/O I/O I/O -- -- I/O I/O -- -- I I O -- O I -- O O O -- -- -- -- I -- O
8/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Pin TQFP100 QFP64 95 96 97 98 99 100 62 -- -- 63 64 -- Symbol DVDD2 NC NC VREGOUT VBG NC I/O -- -- -- -- -- --
When PDNB = "0" -- -- -- -- -- --
Description Digital power supply (Unused) (Unused) Internal regulator voltage output pin (approx. 2.5 V) Internal regulator reference voltage output pin (Unused)
9/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ABSOLUTE MAXIMUM RATINGS
Parameter Analog power supply voltage Digital power supply voltage Analog input voltage Digital input voltage Output current Power dissipation Storage temperature Symbol AVDD DVDD VAIN VDIN1 VDIN2 IO PD Tstg Condition -- -- Analog pin Normal digital pin DVDD = 3.0 to 3.6 V 5 V tolerant pin DVDD < 3.0 V -- Ta = 60 C, per package -- Rating -0.3 to +4.6 -0.3 to +4.6 -0.3 to AVDD+0.3 -0.3 to DVDD+0.3 -0.3 to +6.0 -0.3 to DVDD+0.3 -20 to +20 350 -65 to +150 Unit V V V V V V mA mW C
RECOMMENDED OPERATING CONDITIONS
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit AVDD -- 3.0 3.3 3.6 V DVDD -- 3.0 3.3 3.6 V Ta -- -20 -- 60 C DVDD+ 0.75 x V -- VIH1 Normal digital pin 0.3 DVDD 0.75 x -- 5.5 V VIH2 5 V tolerant pin DVDD 0.19 x V VIL Digital pin -0.3 -- DVDD tIR Digital pin -- 2 20 ns tIF Digital pin -- 2 20 ns CDL Digital pin -- -- 50 pF RDL Pull-up resistance, PCMO 500 -- -- Cvref Between AVREF-AGND 2.2+0.1 -- 4.7+0.1 F Cvout Between VREGOUT-DGND -- 10+0.1 -- F CVBG Between VBG-DGND -- 150 -- pF Fmck MCK -0.01% 12.288 +0.01% MHz Fbclk BCLK (at input) 64 -- 2048 kHz Fsync DRCLK tBS tSB tWS SYNC (at input) MCK, BCLK (at input) BCLK to SYNC (at input) SYNC to BCLK (at input) SYNC (at input) -- 40 100 100 1BCLK 8.0 50 -- -- -- -- 60 -- -- 100 kHz % ns ns s
Parameter Analog power supply voltage Digital power supply voltage Operating temperature range Digital high-level input voltage
Digital low-level input voltage Digital input rise time Digital input fall time Digital output load capacitance Digital output load resistance AVREF bypass capacitor VREGOUT bypass capacitor VBG bypass capacitor Master clock frequency PCM shift clock frequency PCM synchronous signal frequency Clock duty ratio PCM synchronous timing PCM synchronous signal width
(Note) On power-on/shut-down sequence For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up is difficult due to the power supply circuit configuration, power them up in the order of DVDD AVDD. The power supplies should be shut down in the reverse order of power-on sequence.
10/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
ELECTRICAL CHARACTERISTICS
DC Characteristics
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit Standby state -- 200 500 A ISS (PDNB = "0", DVDD = AVDD=3.3 V, Ta = 25C) Operating status 1 Speech CODEC activated/PCM I/F not used -- 45 55 mA IDD1 SC_EN = "1", AFEA_EN = "0", AFEB_EN = "1", XI, XO: 12.288 MHz crystal connected Operating status 2 Speech CODEC activated/PCM I/F used SC_EN = "1",PCMI1_EN = "1", PCMO1_EN -- 50 65 mA IDD2 = "1", AFEA_EN="0", AFEB_EN="0" XI, XO: 12.288 MHz crystal connected IIH Vin = DVDD -- 0.01 10 A IIL Vin = DGND -10 -0.01 -- A IOZH Vou = DVDD -- 0.01 10 A IOZL Vout = DGND Digital input pins, I/O pin IOH = 4.0 mA IOH = 0.5 mA (XO pin) IOH = 1 2.0 mA (CLKOUT pin) Digital output pins, I/O pin IOL = -4.0 mA IOL = -0.5 mA (XO pin) IO = -12.0 mA (CLKOUT pin) Open drain output pins IOL = -12.0 mA Input pins I/O pins -10 0.78 x DVDD -- -- A
Parameter
Power supply current
Digital input pin Input leakage current Digital I/O pin Output leakage current High-level output voltage
VOH
--
--
V
Low-level output voltage
VOL1
--
--
0.4
V
VOL2 Input capacitance (*1) CIN1 CIN2
-- -- --
-- 6 10
0.4 -- --
V pF pF
*1 Design guaranteed value
11/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Analog Interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1 ,2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit RIN AIN0N, AIN0P, AIN1N 10 -- -- M RL GSX0, GSX1, VFRO0, VFRO1 10 -- -- k CL Analog output pins -- -- 50 pF VOF VFRO0, VFRO1 -40 -- 40 mV GSX0, GSX1, VFRO0, VFRO1 1.158 1.3 1.458 Vpp VO RL = 10k, AMP input 1.3 Vpp
Parameter Input resistance (*1) Output load resistance Output load capacitance Offset voltage Output voltage level (*2)
*1 Design guaranteed value *2 -7.7 dBm (600) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
12/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AC Characteristics in Speech CODEC = G.711 (-law) Mode
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit Frequency (Hz) Level (dBm0) 0 to 60 25 -- -- dB 300 to 3000 -0.15 -- 0.20 dB 1020 Reference -- 0 3300 -0.15 -- 0.80 dB 3400 0 -- 0.80 dB 3968.75 13 -- -- dB 0 to 3000 -0.15 -- 0.20 dB 1020 Reference -- 0 3300 -0.15 -- 0.80 dB 3400 0 -- 0.80 dB 3968.75 13 -- -- dB 3 35 -- -- dBp 0 35 -- -- dBp 1020 -30 35 -- -- dBp -40 28 -- -- dBp -45 23 -- -- dBp 3 35 -- -- dBp 0 35 -- -- dBp 1020 -30 35 -- -- dBp -40 28 -- -- dBp -45 23 -- -- dBp 3 -0.2 -- 0.2 dB -10 Reference -- 1020 -40 -0.2 -- 0.2 dB -50 -0.6 -- 0.6 dB -55 -1.2 -- 1.2 dB 3 -0.2 -- 0.2 dB -10 Reference -- 1020 -40 -0.2 -- 0.2 dB -50 -0.6 -- 0.6 dB -55 -1.2 -- 1.2 dB Analog input = -- -- -70 dBm0p -- AVREF -- PCMI = "1" -- -- -70 dBm0p 1020 1020 0 0 0.285 0.285 0.320 0.320 0.359 0.359 Vrms Vrms
Parameter
Symbol LT1 LT2 LT3 LT4 LT5 LT6 LR2 LR3 LR4 LR5 LR6 SDT1 SDT2 SDT3 SDT4 SDT5 SDR1 SDR2 SDR3 SDR4 SDR5 GTT1 GTT2 GTT3 GTT4 GTT5 GTR1 GTR2 GTR3 GTR4 GTR5 NIDLT NIDLR AVT AVR
Transmit frequency characteristics
Receive frequency characteristics
Transmit signal-to-noise ratio (*1)
Receive signal-to-noise ratio (*1)
Transmit inter-level loss errors
Receive inter-level loss errors
Idle channel noise (*1) Transmit absolute level (*2) Receive absolute level (*2)
*1 P-message weighted filter used *2 0.320 Vrms = 0 dBm0 = -7.7 dBm (600)
13/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AC Characteristics (Gain Setting) in Speech CODEC = G.711 (-law) mode
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit For all gain set values -1.0 -- 1.0 dB
Parameter Transmit/receive gain setting accuracy
Symbol GAC
AC Characteristics (Tone Output) in Speech CODEC = G.711 (-law) Mode
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit For all frequency set values -1.5 -- 1.5 % For all gain set values -2.0 -- 2.0 dB
Parameter Frequency deviation Output level
Symbol fDFT oLEV
AC characteristics (DTMF Detector and Other Detectors) in Speech CODEC = G.711 (-law) Mode
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit For all detection level set values -2.5 -- 2.5 dB
Parameter Detection level accuracy
Symbol dLAC
AC characteristics (Echo Canceler)
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit -- -- 35 -- dB -- -- -- 32 ms
Parameter Echo attenuation Erasable echo delay time
Symbol eRES tECT
Measuring method
Echo Canceler ATT E.R.L (echo return loss) LPF 5kHz White noise generator Sin Sout Level Meter
Delay Echo delay time
Rout
Rin
14/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Timings of PDNB, XO, and AVREF
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit tPDNB tAVDDON txtal PDNB pin -- -- AVREF = 1.4 (90%) C5 = 4.7 F, C6 = 0.1 F (See Figure 9) AVREF = 1.4 (90%) C5 = 2.2 F, C6 = 0.1 F (See Figure 9) 250 0 -- -- -- -- -- -- -- -- 20 600 s ns ms ms
Parameter Power-down signal pulse width AVDD supply delay time Oscillation activation time
AVREF rise time
tAVREF
--
--
300
ms
DVDD AVDD
DVDD AVDD tAVDDON VREGOUT
90%
DVDD AVDD 0V Approx. 2.5V 0V DVDD
90%
PDNB tPDNB
0V AVDD
XO 0V txtal AVREF tAVREF Approx. 1.4 V 0V
Figure 1 Timings of PDNB, XO, and AVREF (Note) The capacitance of the AVREF capacitor (C5) affects the AVREF rise time and analog characteristics. If weight is given to the analog characteristics, specify 4.7 F, and if it is given to the AVREF rise time, specify 2.2 F. The electrical characteristics for the analog characteristics that are described above are guaranteed in both capacitances.
15/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PCM interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit fBCLK CDL = 20 pF (during output) -0.1% 2.048 +0.1% MHz dBCLK CDL = 20 pF (during output) 45 50 55 % fSYNC CDL = 20 pF (during output) -0.1% 8 +0.1% kHz dSYNC CDL = 20 pF (during output) 45 50 55 % 1 BCLK = 2.048 MHz At output tBS BCLK to SYNC (during output) 100 -- -- ns tSB SYNC to BCLK (during output) 100 -- -- ns tDS 50 -- -- ns PCMI pin tDH 50 -- -- ns tSDX -- -- 100 ns PCMO pin tXD1 -- -- 100 ns Pull-up resistance RDL = 500 tXD2 -- -- 100 ns CDL = 50 pF -- -- 100 ns tXD3
3 4 5 6 7 8 16
Parameter Bit clock frequency Bit clock duty ratio Synchronous signal frequency Synchronous signal duty ratio Transmit/receive synchronous timing Input setup time Input hold time Digital output delay time Digital output hold time
BCLK
0 tBS
1 tSB
2
tWS
SYNC
tDS tDH LSB G.711 LSB 16-bit linear
PCMI
MSB
Figure 2 PCM Interface Input Timing (Long Frame)
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
-
17
tWS
SYNC
tDS tDH LSB G.711 LSB 16-bit linear
PCMI
MSB
Figure 3 PCM Interface Input Timing (Short Frame)
16/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
-
17
tWS
SYNC
tXD1 tXD2 LSB G.711 tXD3 LSB 16-bit linear tXD3
PCMO
tSDX
MSB
Figure 4 PCM Interface Output Timing (Long Frame)
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
10
-
18
tWS
SYNC
tXD1 tXD2 LSB G.711 tXD3 LSB 16-bit linear tXD3
PCMO
MSB
Figure 5 PCM Interface Output Timing (Short Frame)
17/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Control Register Interface
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta= -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit tRAS 10 -- -- ns tRAH 0 -- -- ns tWAS 10 -- -- ns tWAH 10 -- -- ns tWDS 20 -- -- ns tWDH 10 -- -- ns tRCS 10 -- -- ns CL = 50 pF tRCH 0 -- -- ns tWCS 10 -- -- ns tWCH 10 -- -- ns tWW 10 -- -- ns tRDD -- -- 20 ns tRDH 3 -- -- ns tRW 25 -- -- ns tCD 10 -- -- ns
Parameter Address setup time (at Read) Address hold time (at Read)) Address setup time (at Write) Address hold time (at Write) Write data setup time Write data hold time CSB setup time (at Read) CSB hold time (at Read) CSB setup time (at Write) CSB hold time (at Write) WRB pulse width Read data output delay time Read data output hold time RDB pulse width CSB disable time
A7-A0 Input D7-D0 Inputoutput CSB Input tWCS WRB Input tWAS
A1 tWAH tRAS
A2 tRAH D2 Output tRDD tRDH
D1 Input tWDS tWDH
tWCH
tCD
tRCS
tRCH
tWW RDB Input Write timing
tRW
Read timing
Figure 6 Control Register Interface
18/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Transmit/Receive Buffer Interface (Frame Mode)
(AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Condition Min. Typ. Max. Unit 3 -- -- ns -- -- 20 ns 10 -- -- ns 0 -- -- ns 10 -- -- ns 10 -- -- ns 20 -- -- ns 10 -- -- ns 10 -- -- ns CL = 50 pF 0 -- -- ns 10 -- -- ns 10 -- -- ns 10 -- -- ns 3 -- -- ns -- -- 20 ns -- -- 30 ns 3 -- -- ns 35 -- -- ns 10 -- -- ns
Parameter FR1B setup time FR1B output delay time Address setup time (at Read) Address hold time (at Read)) Address setup time (at Write) Address hold time (at Write) Write data setup time Write data hold time CSB setup time (at Read) CSB hold time (at Read) CSB setup time (at Write) CSB hold time (at Write) WRB pulse width FR0B setup time FR0B output delay time Read data output delay time Read data output hold time RDB pulse width CSB disable time
Symbol tF1S tF1D tRAS tRAH tWAS tWAH tWDS tWDH tRCS tRCH tWCS tWCH tWW tF0S tF0D tRDD tRDH tRW tCD
FR0B Output tF0S FR1B Output tF1S A7-A0 Input D15-D0 Inputoutput CSB Input WRB Input tWCS tWCH tCD tRCS tRCH tWAS D1 Input tWDS tWDH tRDD A1 tWAH tRAS tF1D A2 tRAH D2 Output tRDH tF0D
tWW RDB Input Write timing
tRW
Read timing
Figure 7 Transmit/Receive Buffer Interface (Frame Mode)
19/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Transmit/Receive Buffer Interface (DMA Mode)
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to 60C unless otherwise specified) Symbol Condition Min. Typ. Max. Unit tDR1S 3 -- -- ns tDR1RD -- -- 30 ns tDR1FD -- -- 30 ns tRAS 10 -- -- ns tRAH 0 -- -- ns tWAS 10 -- -- ns tWAH 10 -- -- ns tWDS 20 -- -- ns tWDH 10 -- -- ns tAK0S 10 -- -- ns CL = 50 pF tAK0H 0 -- -- ns tAK1S 10 -- -- ns tAK1H 10 -- -- ns tWW 10 -- -- ns tDR0S 3 -- -- ns tDR0RD -- -- 30 ns tDR0FD -- -- 30 ns tRDD -- -- 30 ns tRDH 3 -- -- ns tRW 35 -- -- ns tAD 10 -- -- ns
Parameter DMARQ1B setup time DMARQ1B output delay time Address setup time (at Read) Address hold time (at Read)) Address setup time (at Write) Address hold time (at Write) Write data setup time Write data hold time ACK0B setup time ACK0B hold time ACK1B setup time ACK1B hold time WRB pulse width DMARQ0B setup time DMARQ0B output delay time Read data output delay time Read data output hold time RDB pulse width ACKB disable time
DMARQ0B Output tDR0S tDR0RD DMARQ1B Output tDR1S tDR1RD A7-A0 Input D15-D0 Inputoutput ACK0B Input tAK0S ACK1B Input WRB Input tAK1S tAK1H tAD tAK0H tWAS D1 Input tWDS tWDH tRDD A1 tWAH tRAS D2 Output tRDH tDR1FD A2 tRAH tDR0FD
tWW RDB Input Write timing
tRW
Read timing
Figure 8 Transmit/Receive Buffer Interface (DMA Mode)
20/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PIN FUNCTIONAL DESCRIPTION
AIN0N, AIN0P, GSX0, AIN1N, and GSX1 These are transmit analog input and transmit gain adjustment pins. AIN0N and AIN1N are connected to inverted input pins of internal transmission amplifiers AMP0 and AMP1, and AIN0P is connected to a noninverting input pin of AMP0. GSX0 and GSX1 are connected to output pins of AMP0 and AMP1. See Figure 9 for the gain adjustment. At power down (PDNB = "0" or SPDN = "1"), outputs of GSX0 and GSX1 are in a high impedance state. When the application does not use AMP0, short-circuit GSX0 and AIN0N and connect AIN0P with AVREF. When not using AMP1, short-circuit GSX1 and AIN1N.
VFRO0 and VFRO1 These are receive analog output pins. VFRO0 and VFRO1 are connected to output pins of amplifiers AMP2 and AMP3. Output of output signals, VFRO0 and VFRO1, can be selected using the VFRO0 selection register (VFRO0_SEL) and VFRO1 selection register (VFRO1_SEL): When output is selected ("1"), the receive signal is output and when output is not selected ("0"), AVREF (about 1.4 V) is output. In power down mode, these output pins are set to a high impedance state. It is recommended to use output signals through a DC coupling capacitor. (Note) If output selection is changed while the conversation is in progress, a micronoise is generated. Therefore, it is recommended to select output before starting a call and then start a call. Before canceling reset or resetting, it is recommended to select output of VFRO0 and VFRO1 to the AVREF output side.
GSX1 Gain = R4/R3 <=32(+30dB) R3 : Variable R4 : 500k Max. R4 C2 R3 AIN1N 10k
A/D1
AMP1 VFRO1_SEL
Out : 1.3Vp-p Max.
C4
VFRO1
10k AMP3
D/A1
GSX0 R2 Gain = R2/R1 <= 32(+30dB) R1 : Variable R2 : 500k Max. C1 R1 AIN0N AIN0P 10k
A/D0
AMP0
Out : 1.3Vp-p Max.
C3 VFRO0
10k AMP2
VFRO0_SEL
D/A0
AVREF C5 + 2.2 to 4.7F
VREF
C6 0.1F
Figure 9 Analog Interface
21/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AVREF This is an output pin of an analog signal ground potential. With the output potential of about 1.4 V, insert bypass capacitors of 2.2 to 4.7 F (aluminum electrolysis type) and 0.1 F (ceramic type) in parallel. AVREF outputs 0.0 V at power down. AVREF starts being powered up after power-down reset, the system restarts from ( PDNB = "1" and SPDN = "0"). XI and XO These are the master clock input pin (XI) and the crystal connection pins for the master clock (XI and XO). Oscillation stops at power down by PDNB or software power down by SPDN. Oscillation starts after power-down is reset and the clock is supplied to the LSI internal section after oscillation stabilization delay time has elapsed (about 21.3 ms). Figure 10 shows a master clock input example.
CR0-B7 (SPDN) PDNB
To the internal section
CR0-B7 (SPDN) PDNB
To the internal section
XI
R Crystal
XO
CLKOUT
XI 12.288 MHz
XO Open
CLKOUT
Provisional C1 C2 Crystal (12.288 MHz) Kyocera Kinseki Corp. HC-49/U-S [CL=12pF] C1 8 pF C2 8 pF R 1 M
Figure 10 Example of an Oscillation Circuit and Clock Input
CLKOUT This is a 12.288 MHz master clock output pin. (Provided for 100-pin packages only) Since output is disabled in the initial state, set the 12.288 MHz clock output enable control register (CLKOUT_EN) to "1" when clock output is required. PDNB This is a power-down control input pin. A power-down state can be set by setting this pin to "0". This pin also functions as an LSI reset pin. To prevent an LSI operation error, use PDNB for the initial power-down reset after power is applied. To put the LSI into a power-down state, fix PDNB to "0" for 250 s or more. LSI power-down reset can be performed by setting the software power down reset control register SPDN to "0" "1" "0". Power-down is released, the initial mode display register (READY) is set to "1" after 200 ms, and various function setting modes (initial modes) are entered. See Figure 1 for the timings of PDNB, AVREF, XO, and the initial mode. (Note) Turn on the power in a power-down state by PDNB. When using the LSI by inputting a master clock to the XI pin, first maintain the power-down state (PDNB = 0) until power is applied to the digital power supply (DVD0, 1, and 2) and the analog power supply (AVDD) (90% or more) and the master clock is input to the XI pin, then release the power-down state (PDNB = 0 1) . In this case also, fix PDNB to "0" for 250 s or more.
22/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
DVDD0, DVDD1, DVDD2, and AVDD These are power supply pins. DVDD0, DVDD1, and DVDD2 are connected to the power supply of a digital circuit and AVDD is connected to a power supply of an analog circuit. Connect these pins near the LSI and insert bypass capacitors of 10 F (electrolysis type) and 0.1 F (ceramic type) between DGND and AGND in parallel. DGND0, DGND1, DGND2, and AGND These are ground pins. DGND0, DGND1, and DGND2 are connected to grounds of digital circuits and AGND is connected to a ground of an analog circuit. Connect these pins near the LSI. VREGOUT This is an output pin of an internal regulator voltage (about 2.5 V). Connect a capacitor of about 0.1 F (ceramic type) in parallel to about 10 F (ceramic or tantalum type) between this pin and a ground pin. VBG This is a reference output pin for an internal regulator. Connect a laminated ceramic capacitor of about 150 pF between this pin and a ground pin. TST0 and TST1 These are input pins for testing. At normal use, input "0".
23/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
INTB/GPIOA[6] Primary function: INTB This in an interrupt request output pin. When the interrupt cause is changed, this pin outputs a "L" level for about 1.0 s. When the interrupt factor is not changed, "H" is output. The interrupt factor can be checked by reading CR16-CR22. Table 1 lists the interrupt causes. The interrupt causes can be masked individually in the internal memory (interrupt cause mask control).
Table 1 Interrupt Causes
CR BIT B2 CR16 B1 B0 CR17 CR18 B0 B0 B7 B4 CR19 B3 B2 B1 B6 CR20 B4 B3-B0 B3 B2 CR21 B1 B0 B3 B2 CR22 B1 B0 Register name FSK receive overrun error notification register (FDET_OER) FSK receive framing error notification register (FDET_FER) FSK receive data read request notification register (FDET_RQ) FSK output data setting completion flag (FGEN_FLAG) Timer overflow display register (TMOVF) DSP status register (DSP_ERR) TONE1 detector detection status register (TONE1_DET) TONE0 detector detection status register (TONE0_DET) TGEN1 execution flag display register (TGEN1_EXFLAG) TGEN0 execution flag display register (TGEN0_EXFLAG) Dial pulse detector detection status register (DP_DET) DTMF detector detection status register (DTMF_DET) DTMF code display register (DTMF_CODE[3:0]) CH2 transmit error status register (TXERR_CH2) CH1 transmit error status register (TXERR_CH1) CH2 transmit request notification register (FR0_CH2) CH1 transmit request notification register (FR0_CH1) CH2 receive error status register (RXERR_CH2) CH1 receive error status register (RXERR_CH1) Receive invalid write error notification register (RXBW_ERR) Receive request notification register (FR1) Rising edge Falling edge x x x x x x Remarks
x x
x
: With INTB interrupt generation function
x: Without INTB interrupt generation function
Secondary function: GPIOA[6] When the primary function/secondary function selection register (GPFA[6]) of GPIOA[6] is set to "1", this pin functions as a general-purpose I/O port GPIOA[6].
24/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
A0-A7 These are address input pins for accessing a frame/DMA/control register. Each address is as follows. Transmit buffer (TX Buffer) A7-A0 = 80h Receive buffer (RX Buffer) A7-A0 = 81h Control register (CR) See Tables 5 to 8 for the addresses. D0-D15 These are data I/O pins for accessing a frame/DMA/control register. Since these pins are I/O pins, connect pull-up resistors. When an 8-bit bus access is selected in the MCU interface data width selection register (BW_SEL), pins D0-D7 are enabled. When using the pins with 8-bit bus access (BW_SEL = "1"), fix the input of high-order D8-D15 to either "0" or "1" since they are constantly in an input state. CSB This is a chip select input pin for accessing a frame/control register. RDB This is a read enable input pin for accessing a frame/DMA/control register. WRB This is a write enable input pin for accessing a frame/DMA/control register.
25/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
FR0B (DMARQ0B) * FR0B (FRAME/DMA selection register FD_SEL = "0" in frame mode) This is a transmit frame output pin that outputs data when the transmit buffer for frame access becomes full. When the transmit buffer becomes full, the pin outputs "L" and retains "L" until the specified number of words are read from the MCU. * DMARQ0B (FRAME/DMA selection register FD_SEL = "1" in DMA mode) This is a DMA request output pin that outputs data when the transmit buffer for DMA access becomes full. When the transmit buffer becomes full, the pin outputs "L" and the value is reset to "H" automatically when an acknowledgment signal (ACK0B = "0") and the fall of a read enable signal (RDB = "1" "0") are received from the MCU side. This operation is repeated until the specified number of words are read from the MCU. FR1B (DMARQ1B) * FR1B (FRAME/DMA selection register FD_SEL = "0" in frame mode) This receive frame output pin outputs data when the receive buffer for frame access becomes empty. When the receive buffer becomes empty, the pin outputs "L" and retains "L" until the specified number of words are written from the MCU. * DMARQ1B (FRAME/DMA selection register FD_SEL = "1" in DMA mode) This a DMA request output pin that outputs data when the receive buffer for DMA access becomes empty. When the receive buffer becomes empty, the pin outputs "L" and the value is reset to "H" automatically when an acknowledgment signal (ACK1B = "0") and the fall of a write enable signal (WRB = "1" "0") are received from the MCU side. This opeation is repeated until the specified number of words are written from the MCU side. ACK0B/GPIOA[4] Primary function: ACK0B This is a DMA acknowledgment input pin for DMARQ0B for transmit buffer DMA access; it is enabled in DMA mode (FD_SEL = "1"). When using the pin in frame mode (FD_SEL = "0"), fix this pin to "1". Secondary function: GPIOA[4] When the primary function/secondary function registration register (GPFA[4]) of GPIOA[4] is set to "1", the pin functions as a general-purpose I/O port GPIOA[4].
ACK1B/GPIOA[5] Primary function: ACK0B This is a DMA acknowledgment input pin for DMARQ1B for receive buffer DMA access; it is enabled in DMA mode (FD_SEL = "1"). When using this pin in frame mode (FD_SEL = "0"), fix this pin to "1". Secondary function: GPIOA[5] When the primary function/secondary function registration register (GPFA[5]) of GPIOA[5] is set to "1", the pin functions as a general-purpose I/O port GPIOA[5].
GPIOA[0], GPIOA[1], GPIOA[2], and GPIOA[3] These are general-purpose I/O ports A[3:0]. However, the following secondary functions are assigned to GPIOA[0] and GPIOA[2]. Secondary function of GPIOA[0]: Input pin (DPI) of a dial pulse detecter (DPDET) Secondary function of GPIOA[2]: Output pin (DPO) of a dial pulse transmitter (DPGEN)
26/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
GPIOB[5:0] This is a general-purpose I/O port B[5:0]. (Provided for 100-pin packages only.) GPIOC[7:0] This is a general-purpose I/O port C[7:0]. (Provided for 100-pin packages only.) CLKSEL This is an input-output control input pin of SYNC and BCLK. The pin controls input when it is set to "0" and output when it is set to "1". SYNC This is a 8 kHz synchronous signal I/O pin of PCM signals. When CLKSEL is "0", constantly input an 8 kHz clock synchronized with BCLK. When CLKSEL is "1", this pin outputs an 8 kHz clock synchronized with BCLK. When the SYNC frame control register (SYNC_SEL) is "0", long frame synchronization is specified and when the register is "1", short frame synchronization is specified. BCLK This is a shift clock I/O pin of a PCM signal. When CLKSEL is "0", clock input synchronized with SYNC is necessary. When G.711 is selected, input a clock of 64 kHz to 2.048 MHz and when 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz. When CLKSEL is "1", this pin outputs a clock of 2.048 MHz synchronized with SYNC. (Remarks) Table 2 shows the input-output control of SYNC and BCLK and the frequencies. Table 2 SYNC and BCLK Input-Output Control
CLKSEL SYNC Input (8 kHz) Output (8 kHz) BCLK Input (64 kHz to 2048 kHz) Output (2.048 MHz) Remarks Always input a clock after start of power supply. When G.711 is selected, input a clock of 64 kHz to 2.048 MHz. When 16-bit linear is selected, input a clock of 128 kHz to 2.048 MHz. At power down, "L" is output.
"0"
"1"
PCMO This is a PCM signal output pin. A PCM signal is output synchronized with the rise of BCLK or SYNC. For the output from PCMO, data is output to only the applicable time slot section according to the selected coding format and the setting of the time slot position and other sections are set to a high-impedance state. If a PCM interface is not used, PCMO is set to a high impedance state. (Note) Be sure to connect a pull-up resistor externally to the PCMO pin, because the pin is an open drain output pin. Do not use a pull-up voltage greater than the digital power supply voltage (DVDD). PCMI This is a PCM signal input pin. The signal is shifted at falling of BCLK and is input from MSB. If a PCM interface is not used, fix the input to "0" or "1".
27/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
FUNCTIONAL DESCRIPTION
Transmit and receive buffers
CONFIGURATION EXAMPLES
Configuration Example 1 (Basic Call, CODEC_A)
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN_PCM1 RX_SIG PCM_TXEN1 Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN PCM0 GSX0 10k AIN0N AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + ATTs Center Clip GPAD Sout SC_TXEN TXGAIN Encoder _CH1 G.711 TXDETA PCM_RXEN0 TXGEN TXGAIN_SC G.729.A CH1 T S W CH2 DC_EN Linear PCM Codec (CODEC_A) _CH2 STGAINA AFF Echo Canceller RX1T _GAIN RX2TX1 _GAIN Speech Codec Bus Control Unit TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB D0-D15 RXGAINA VFRO0 AMP2 D/A0 LPF CODECA_RXEN RXGENA RXGEN SC_RXEN RXDET RX_SIG AVREF VREF Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET0 TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/ D) TGEN0_EXFLAG TONE_GEN0 (TONE A/ B) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGENB_EN RXGEN DPDET DPGEN TIMER TIMOVF GPIO2 Control Register RXGAIN _CH2 Rout ATTr Rin RXGAIN_SC RXGAIN _CH1 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
AIN0P
10k
GPIO0 DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8 6 GPIOB [5:0] 4 GPIOA [3:0]
INTB/ GPIOA[6]
CLKOUT
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by connecting the analog telephone interface on the Linear PCM CODEC_A side.
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
ML7204 (Configuration example 1)
RX_SIG
GPIOC [7:0]
XO
PDNB
XI
TST0
TST1
VoIP-NW
28/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 2 (Basic Call, CODEC_B)
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN PCM1 RX_SIG PCM_TXEN1 Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 PCM_RXEN0 GSX0 10k AIN0N AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + - ATTs Center Clip GPAD Sout SC_TXEN TXGAIN Encoder G.711 TXGAIN _CH2 STGAINA AFF Echo Canceller RX1TX2 _GAIN TXDETA TXGEN TXGAIN_SC G.729.A CH1 T S W CH2 TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB Bus Control Unit RDB CSB D0-D15 RXGAINA VFRO0 AMP2 D/A0 LPF CODECA RXGEN RXGEN SC_RXEN RXDET RX_SIG AVREF VREF TIMER Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET0 TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFL TONE_GEN1 (TONE) TGEN0_EXFLAG TONE_GEN0 (TONE) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGEN DPGEN TIMOVF GPIO2 Control Register Rout ATTr Rin RXGAIN_S RXGAIN _CH1 RXGAIN _CH2 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
AIN0P
Linear PCM (CODEC_A)
DC_EN RX2TX1 _GAIN Speech Codec
10k
GPIO0 DPDET DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8
RXGENB_EN
INT
INTB/ GPIOA[6]
6 GPIOB [5:0]
4 GPIOA [3:0]
CLKOUT
XO
PDNB
This example shows the configuration for making calls with an analog telephone set (A-TEL) on the NW side by connecting the analog telephone interface on the Linear PCM CODEC_B side.
RX_SIG Linear PCM Codec
(CODEC_B)
A-TEL
PCM Codec
PCM I/F
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
VoIP-NW
ML7204 (Configuration example 2)
RX_SIG
GPIOC [7:0]
XI
TST0
TST1
29/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 3 (Calling Using Extension with PCM)
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN_PCM1 PCM_TXEN1 RX_SIG Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 PCM_RXEN0 GSX0 10k AIN0N AIN0P AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + ATTs Center Clip GPAD Sout SC_TXEN TXDETA TXGEN TXGAIN_SC G.729.A TXGAIN Encoder _CH1 G.711 TXGAIN _CH2 RX1TX2 _GAIN RX2TX1 _GAIN CH1 T S W CH2 DC_EN Bus Control Unit TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB 10k RXGAINA VFRO0 AMP2 D/A0 LPF CODECA_RXEN RXGENA RXGEN SC_RXEN RXD300ET RX_SIG AVREF VREF Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET0 TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/ D) TGEN0_EXFLAG TONE_GEN0 (TONE A/ B) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGENB_EN RXGEN TIMER DPGEN TIMOVF GPIO2 GPIO0 DP DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8 GPIOC [7:0] CLKOUT XO PDNB XI 6 GPIOB [5:0] 4 GPIOA [3:0] Control Register Rout ATTr Rin RXGAIN_S D0-D15 RXGAIN _CH1 RXGAIN _CH2 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
Linear PCM Codec (CODEC_A)
STGAINA
AFF
Echo Canceller
Speech Codec
DPDET
INT
INTB/ GPIOA[6]
TST0
TST1
30/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
This example shows the configuration for making calls using extension between two analog telephone sets (A-TEL1 and A-TEL2) on the equipment that has two or more analog telephone interface ports.
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL1
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
ML7204 (Configuration example 3)
RX_SIG
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL2
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
ML7204 (Configuration example 3)
RX_SIG
31/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 4 (Three-Way Calling: Terminal Side [Two Parties] - NW Side [One Party])
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN_PCM1 PCM_TXEN1 RX_SIG Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 PCM_RXEN0 GSX0 10k AIN0N AIN0P AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + ATTs Center Clip GPAD Sout SC_TXEN TXDETA TXGEN TXGAIN_SC TXGAIN CH1 G.729.A Encoder G.711 TXGAIN _CH2 STGAINA AFF Echo Canceller RX1TX2 _GAIN RX2TX1 _GAIN CH1 T S W CH2 DC_EN Bus Control Unit TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB 10k RXGAINA VFRO0 AMP2 D/A0 LPF CODECA_RXEN RXGENA RXGEN SC_RXEN RXDET RX_SIG AVREF VREF Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER TONE_DET0 PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/D) TGEN0_EXFLAG TONE_GEN0 (TONE A/B) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGENB_EN RXGEN DPDET DPGEN TIMER TIMOVF GPIO2 Control Register Rout ATTr Rin RXGAIN_SC D0-D15 RXGAIN _CH1 RXGAIN _CH2 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
Linear PCM Codec (CODEC_A)
Speech Codec
GPIO0 DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8 6 GPIOB [5:0] 4 GPIOA [3:0]
INTB/ GPIOA[6]
CLKOUT
TST1
XO
GPIOC [7:0]
XI
PDNB
TST0
32/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
This example shows the configuration for making three-way calling between the terminal side (two parties) and the VoIP NW side (one party).
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL2
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
ML7204 (Configuration example 3)
RX_SIG
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL1
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
VoIP-NW
ML7204 (Configuration example 4)
RX_SIG
33/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 5 (Three-Way Calling: Terminal Side [One Party] - NW Side [Two Parties])
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN_PCM1 PCM_TXEN1 RX_SIG Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 PCM_RXEN0 GSX0 10k AIN0N AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + ATTs Center Clip GPAD Sout SC_TXEN TXGAIN Encoder G.711 TXGAIN _CH2 STGAINA AFF Echo Canceller RX1TX2 _GAIN RX2TX1 _GAIN TXDETA TXGEN TXGAIN_SC G.729.A CH1 T S W CH2 DC_EN Bus Control Unit TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB D0-D15 RXGAINA VFRO0 AMP2 D/A0 LPF CODECA_RXEN RXGENA RXGEN SC_RXEN RXDET RX_SIG AVREF VREF TIMER Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET0 TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/D) TGEN0_EXFLAG TONE_GEN0 (TONE A/B) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGEN DPGEN TIMOV GPIO Control Register Rout ATTr Rin RXGAIN_SC RXGAIN _CH1 RXGAIN _CH2 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
AIN0P
Linear PCM Codec (CODEC_A)
Speech Codec
10k
DPDET
GPIO DP D DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
RXGENB_EN
INT
FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8 6 GPIOB [5:0] 4 GPIOA [3:0]
INTB/ GPIOA[6]
CLKOUT
PDNB
XO
TST0
TST1
This example shows the configuration for making three-way calling between the terminal side (one party) and VoIP NW side (two parties).
RX_SIG
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A-TEL
Linear PCM Codec
(CODEC_A)
VoIP-NW1
EC Speech Codec MCU I/F
VoIP-NW2
RX_SIG
ML7204 (Configuration example 5)
GPIOC [7:0]
XI
34/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 6 (Three-Way Calling: Terminal Side [Three Parties])
GSX]1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 TXGAIN_PCM1 RX_SIG PCM_TXEN1 Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 PCM_RXEN0 GSX0 10k AIN0N AMP A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + - ATTs Center Clip GPAD Sout SC_TXEN TXGAIN _CH1 Encoder G.711 TXGAIN _CH2 STGAINA AFF Echo Canceller RX1TX2 _GAIN RX2TX1 _GAIN TXDETA TXGEN TXGAIN_SC G.729.A CH1 T S W CH2 DC_EN Bus Control Unit TX Buffer0 TX Buffer1 RXGAIN_PCM1 PCM_RXEN1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB D0-D15 RXGAINA VFRO0 AMP D/A0 LPF CODECA_RXEN RXGENA RXGEN RXDET RX_SIG AVREF VREF TIMER Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET0 TONE_DET1 TONE0_DET TONE1_DET TXDETA FSK_DET TXDETB DTMF_REC FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF_DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/ D) TGEN0_EXFLAG TONE_GEN0 (TONE A/ B) FGEN_FLAG FSK_GEN RXGENB_EN RXGEN TXGEN RXGENA_EN RXGENA RXGENB DPGEN TIMOVF GPIO2 Control Register SC_RXEN Rout ATTr Rin RXGAIN_SC RXGAIN _CH1 RXGAIN _CH2 G.729.A Decoder G.711 T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
AIN0P
Linear PCM Codec (CODEC_A)
Speech Codec
10k
GPIO0 DPDET DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET FDET_RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8
INT
INTB/ GPIOA[6]
6 GPIOB [5:0]
4 GPIOA [3:0]
PDNB
XO
TST1
CLKOUT
This example shows the configuration for making three-way calling between analog telephones (A-TEL1, A-TEL2, and A-TEL3) on the equipment with multiple analog telephone interface ports.
ML7204 (configuration example 6)
PCM I/F PCM I/F MCU I/F
ML7204 (configuration example 6)
MCU I/F PCM
ML7204 (configuration example 6)
MCU I/F
I/F
Speech Codec
Speech Codec
PCM Codec
RX_SIG
RX_SIG
Speech Codec
PCM Codec
PCM Codec
RX_SIG
RX_SIG
EC
EC
RX_SIG
(CODEC_B)
(CODEC_B)
(CODEC_A)
(CODEC_A)
(CODEC_B)
EC
A-TEL3
A-TEL2
A-TEL1
(CODEC_A)
Linear PCM Codec
Linear PCM Codec
Linear PCM Codec
Linear PCM Codec
Linear PCM Codec
Linear PCM Codec
RX_SIG
GPIOC [7:0]
TST0
XI
35/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Configuration Example 7 (CODEC-A-CODEC-B Loop Back Mode)
GSX1 10k AIN1N AMP1 A/D1 BPF TXGAINB CODECB_TXEN TXDETB LPEN0 TXGAIN_PCM0 PCM_TXEN0 RX_SIG TXGAIN_PCM1 PCM_TXEN1 Encoder G.711 P/S PCMO PCM I/F
SYNC Linear PCM Codec (CODEC_B) STGAINB PCM Codec TS CONT BCLK CLKSEL RXGAIN_ITS1 10k RXGAINB VFRO1 AMP3 D/A1 LPF RXGENB RXGAIN_PCM0 GSX0 10k AIN0N AIN0P AMP0 A/D0 BPF TXGAINA CODECA_TXEN Sin LPAD + - ATTs Center Clip GPAD Sout SC_TXEN TXGAIN _CH1 Encoder G.711 TXGAIN _CH2 Echo Canceller RX1TX2 _GAIN RX2TX1 _GAIN TXDETA PCM_RXEN0 TXGEN TXGAIN_SC G.729.A CH1 T S W CH2 DC_EN Bus Control Unit TX Buffer0 TX Buffer1 ACK1B/ GPIOA[5] ACK0B/ GPIOA[4] FR1B FR0B WRB RDB CSB 10k RXGAINA VFRO0 AMP2 D/A0 LPF CODECA_RXEN RXGENA RXGEN SC_RXEN RXDET RX_SIG AVREF VREF Detector path setting DVDD2 DVDD1 DVDD0 DGND2 DGND1 DGND0 AGND AVDD VREGOUT VGB OSC 12.288 MHz Unused POWER TONE_DET0 PLL CKGN MCK SYNC (8 kHz) RXDET TONE_DET1 TONE0_DET TONE1_DET TXDETA TXDETB DTMF_REC FSK_DET FDET_RQ FDET_FER/FDET_OER FDET_D[7:0] DTMF DET DTMF_CODE[3:0] Generator path TGEN1_EXFLAG TONE_GEN1 (TONE C/ D) TGEN0_EXFLAG TONE_GEN0 (TONE A/ B) FGEN_FLAG FSK_GEN TXGEN RXGENA_EN RXGENA RXGENB RXGENB_EN RXGEN TIMER DPGEN TIMOVF GPIO2 GPIO0 DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET FDET RQ FDET_FER/FDET_OER FGEN_FLAG TIMOVF 8 CLKOUT PDNB GPIOC [7:0] XO 6 GPIOB [5:0] 4 GPIOA [3:0] Control Register Rout ATTr Rin RXGAIN SC D0-D15 RXGAIN _CH1 RXGAIN CH2 Decode G.711 G.729.A T CH1 S W CH2 DC_EN Frame/DMA Controller RX Buffer0 RX Buffer1 16b A0-A7 8b RXGAIN_PCM1 PCM_RXEN1 CODECB_RXEN LPEN1 RXGAIN_ITS2 Decoder G.711 S/P PCMI
Linear PCM Codec (CODEC_A)
STGAINA
AFF
Speech Codec
DPDET
INT
INTB/ GPIOA[6]
TST0
This example shows the configuration where CODEC_A and CODEC_B are connected in loopback mode according to the internal path settings.
TST1
XI
RX_SIG
B
Linear PCM Codec
(CODEC_B)
PCM Codec
PCM I/F
A
Linear PCM Codec
(CODEC_A)
EC
Speech Codec
MCU I/F
ML7204 (Configuration example 7)
RX_SIG
36/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
APPLICATION CIRCUITS
ML7204-001GA
1.4 V 50 51 Analog input 52 53 54 55 2.2uF 0.1uF 56 Analog output 57 45 46 47 48 VFRO0 VFRO1 GPIOA[0] GPIOA[1] GPIOA[2] GPIOA[3] AIN0P AIN0N GSX0 GSX1 AIN1N AVREF A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ACK0B ACK1B FR0B FR1B INTB CSB RDB WRB VBG 7 33 62 49 10uF 0.1uF 16 44 59 58 41 40 39 38 37 36 35 34 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 +3.3 V 8 9 10 11 12 13 14 15 64 150pF 63 0.1uF 10uF
General-purpose I/O pins
MCU I/F
+3.3 V +3.3 V 500 PCM I/F 43 3 4 5 6 42 CLKSEL PCMO PCMI BCLK SYNC PDNB
Power-down control 12.288 MHz crystal
60 61 1M
XI XO
8pF
8pF +3.3 V DVDD0 DVDD1 DVDD2 AVDD DGND0 DGND1 DGND2 AGND
VREGOUT
TST1 TST0
1 2
Conditions * Frame mode * SYNC and BCLK: Configured to be output (CLKSEL = "1")
37/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
1.4 V 78 79 Analog input 80 82 83 85 2.2 F 0.1 F
ML7204-001TB
AIN0P AIN0N GSX0 GSX1 AIN1N AVREF A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 60 59 58 57 56 55 54 53 49 48 46 45 43 42 40 39 37 36 34 33 31 30 28 27 +3.3 V ACK0B ACK1B FR0B FR1B INTB CSB RDB WRB VBG 15 16 19 20 21 22 23 24 99 150 pF 98 0.1 F 10 F
86 Analog output 87 70 71 74 75 62 63 65 66 68 69 4 5 10 11 13 14 17 18 +3.3 V +3.3 V 500 PCM I/F 64 6 7 8 9 92 94 1 M 8 pF 8 pF +3.3 V 12 52 95 76 10uF 0.1uF 25 67 91 88
VFRO0 VFRO1 GPIOA[0] GPIOA[1] GPIOA[2] GPIOA[3] GPIOB[0] GPIOB[1] GPIOB[2] GPIOB[3] GPIOB[4] GPIOB[5] GPIOC[0] GPIOC[1] GPIOC[2] GPIOC[3] GPIOC[4] GPIOC[5] GPIOC[6] GPIOC[7] CLKSEL PCMO PCMI BCLK SYNC XI XO
General-purpose I/O pins A
MCU I/F
General-purpose I/O pins B
General-purpose I/O pins C
12.288 MHz crystal
VREGOUT
PDNB DVDD0 DVDD1 DVDD2 AVDD DGND0 DGND1 DGND2 AGND CLKOUT
61 1
Power-down control 12.288 MHz clock output Conditions * Frame mode * SYNC and BCLK: Configured to be output (CLKSEL = "1")
TST1 TST0
2 3
38/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
39/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
40/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
REVISION HISTORY
Document No.
FEDL7204-001DIGEST-01
Date
Aug. 12, 2004
Page Previous Current Edition Edition
- -
Description
Final edition 1
41/42
FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
42/42

▲Up To Search▲

Price & Availability of ML7204-001

	To Download ML7204-001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .